Semiconductor storage device

ABSTRACT

A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-174787, filed Sep. 19, 2018, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to semiconductor storage devices.

BACKGROUND

As an example of a semiconductor storage device, a cross point semiconductor memory in which a bit line and a word line are alternately stacked is known. In such a semiconductor memory, a wiring layer is provided for electrically connecting memory cells to drive circuits such as selection circuits and non-selection circuits.

DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic plan view of a semiconductor storage device according to a first embodiment.

FIG. 2 illustrates a schematic cross-sectional view of a part of the semiconductor storage device according to the first embodiment.

FIG. 3 illustrates a plan view of the semiconductor storage device according to the first embodiment in a layered manner.

FIG. 4 illustrates a plan view of a semiconductor storage device according to a first comparative example in a layered manner.

FIG. 5A illustrates a plan view of another layout of contacts.

FIG. 5B illustrates a plan view of still another layout of contacts.

FIG. 6 is a diagram schematically illustrating a cross-sectional structure of a semiconductor storage device according to a second embodiment.

FIG. 7 is a diagram schematically illustrating a cross-sectional structure of a semiconductor storage device according to a second comparative example.

DETAILED DESCRIPTION

Embodiments provide a semiconductor storage device capable of reducing the number of wiring layers for electrically connecting memory cells to drive circuits.

In general, according to an embodiment, a semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings extending in a first direction and arranged side by side in a second direction perpendicular to the first direction, fourth and fifth wiring layers, each including a plurality of second wirings extending in the second direction and arranged side by side in the first direction, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, a memory cell array having a plurality of memory cells formed at intersections of the first and second wirings of adjacent wiring layers, a first contact electrically connected to a first wiring of the first wiring layer, in a hook-up region, a second contact electrically connected to a first wiring of the second wiring layer, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, a first drive circuit electrically connected to the first connection wiring, and a second drive circuit electrically connected to the second connection wiring.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited by embodiments described below.

First Embodiment

FIG. 1 illustrates a schematic plan view of a semiconductor storage device according to a first embodiment. FIG. 2 illustrates a schematic cross-sectional view of a part of the semiconductor storage device according to the first embodiment. A semiconductor storage device 1 according to the present embodiment is a cross point semiconductor memory in which a bit line and a word line are alternately stacked.

A cell array 10 is provided in the semiconductor storage device 1. The cell array 10, as shown in FIG. 2, has a plurality of memory cells 11. Each of the memory cells 11 is formed at an intersection portion of a cell wiring 20 and a cell wiring 30.

The cell wiring 20 functions as a bit line extending in an X direction. Meanwhile, the cell wiring 30 functions as a word line extending in a Y direction perpendicular to the X direction. In the present embodiment, the cell wiring 20 corresponds to the first cell wiring and the cell wiring 30 corresponds to the second cell wiring. However, the cell wiring 20 may correspond to the second cell wiring while the cell wiring 30 may correspond to the first cell wiring.

The cell wiring 20 and the cell wiring 30 are alternately stacked in a Z direction perpendicular to the X direction and the Y direction. In the semiconductor storage device 1, a plurality of cell wirings 20 are arrayed in the Y direction in each of three cell wiring layers: BL0, BL1, and BL2. In addition, a plurality of cell wirings 30 are arrayed in the X direction in each of two cell wiring layers: WL0 and WL1. The number of cell wirings formed in each cell wiring layer and the number of cell wiring layers are not particularly limited.

Among the plurality of cell wirings 20, cell wirings 20 a provided in odd-numbered cell wiring layers BL0 and BL2 are electrically connected with contacts 40 in hook-up regions 50 and hook-up regions 51, as shown in FIG. 1. The hook-up region 50 is provided outside the cell array 10 in the X direction. The hook-up region 51 is provided on the opposite side of the cell array 10 from the hook-up region 50.

In addition, a cell wiring 20 b provided in an even-numbered cell wiring layer BL1 is electrically connected to contacts 41 in the hook-up regions 50 and the hook-up regions 51. In each hook-up region, the contacts 40 and the contacts 41 are alternately arranged.

Meanwhile, among the plurality of cell wirings 30, a cell wiring 30 a provided in an odd-numbered cell wiring layer WL0 is connected to contacts 42 in hook-up regions 52 and hook-up regions 53, as shown in FIG. 1. The hook-up region 52 is provided outside the cell array 10 in the Y direction. The hook-up region 53 is provided on the opposite side of the cell array 10 from the hook-up region 52.

In addition, a cell wiring 30 b provided in an even-numbered cell wiring layer WL1 is electrically connected to contacts 43 in the hook-up regions 52 and the hook-up regions 53. In each hook-up region, the contacts 42 and the contacts 43 are alternately arranged.

FIG. 3 illustrates a plan view of the semiconductor storage device 1 according to the first embodiment in a layered manner. Specifically, FIG. 3 shows an XY plane of a layer where the cell wiring layer BL2 is provided, an XY plane of a layer where the cell wiring layer BL1 is wired, an XY plane of a layer where the cell wiring layer BL0 is wired, an XY plane of a layer where the wiring layer D0 is wired, and an XY plane of a layer where a drive circuit layer T is wired, in a vertically aligned manner. In FIG. 3, only the layers electrically connected to the cell wirings 20 are shown and the layers electrically connected to the cell wirings 30 are omitted.

As shown in FIG. 3, the wiring layer D0 is provided below the cell wiring layer BL0 in a direction of a Z-axis. In the wiring layer D0, connection wirings 60 and connection wirings 61 are provided separately from each other in the X direction. In addition, the connection wirings 60 and the connection wirings 61 extend in the direction of the X axis. The connection wirings 60 are electrically connected to the odd-numbered cell wiring layers BL0 and BL2. One ends of the connection wirings 60 are electrically connected to the contacts 40 provided in the hook-up region 51 on the right side of the cell array 10. The contacts 40 are shared by the cell wiring layer BL0 and the cell wiring layer BL2. The other ends of the connection wirings 60 are wired below the cell array 10. The connection wirings 61 are electrically connected to the even-numbered cell wiring layer BL1. One ends of the connection wirings 61 are electrically connected to the contacts 41 provided in the hook-up region 50 on the left side of the cell array 10. The other ends of the connection wirings 61 are wired below the cell array 10. In addition, the one ends of the connection wirings 61 may also be electrically connected to the contacts 41 provided in the hook-up region 51 on the right side of the cell array 10, and the other ends may be arranged below an adjacent cell array 12 in the X direction. FIG. 3 shows an example in which: the wirings in the even-numbered cell wiring layer BL1 in the Y direction extend from the hook-up region 50 on the left side of the cell array 10 to a region below the cell array 10; and the wirings in the odd-numbered cell wiring layer BL1 in the Y direction extend from the hook-up region 51 on the right side of the cell array 10 to a region below the adjacent cell array 12.

The drive circuit layer T is provided below the wiring layer D0. Drive circuits 70 and drive circuits 71 are provided in the drive circuit layer T. Each drive circuit includes a plurality of transistors 72 sharing a gate G. Drains of the transistors provided in the drive circuits 70 are connected to the other ends of the connection wirings 60 through transistor wirings 80. Drains of the transistors provided in the drive circuits 71 are connected to the other ends of the connection wirings 61 through transistor wirings 81. The transistors 72 function as selection transistors or non-selection transistors of the memory cells 11. The selection transistor applies a voltage for writing or reading to a cell wiring connected to a memory cell which is a target of writing or reading, and the non-selection transistor applies a voltage for non-selection to a cell wiring connected to a memory cell which is not the target of writing or reading.

FIG. 4 illustrates a plan view of a semiconductor storage device 100 according to a first comparative example in a layered manner. Constituent elements similar to those of the semiconductor storage device 1 according to the above-described first embodiment are attached with the same reference numerals, and detailed description thereof will be omitted.

In the semiconductor storage device 100 shown in FIG. 4, a wiring layer D1 is provided in addition to the wiring layer D0. The wiring layer D1 includes the connection wirings 60. The connection wirings 60 are electrically connected to the contacts 40 provided in the hook-up region 51 on the right side of the cell array 10.

Meanwhile, the wiring layer D0 includes the connection wirings 61. The connection wirings 61 are electrically connected to the contacts 41 provided in the hook-up region 51 on the right side of the cell array 10.

In the semiconductor storage device 100 according to this comparative example, the connection wirings 60 and the connection wirings 61 are separately provided in the different wiring layers D0 and D1. Therefore, two wiring layers are required in order to electrically connect the memory cells 11 to the drive circuits 70 and 71.

To the contrary, in the semiconductor storage device shown in FIG. 3, the connection wirings 60 and the connection wirings 61 are provided in the same wiring layer D0. That is, the connection wirings 60 and the connection wirings 61 share the wiring layer D0. Therefore, in the semiconductor storage device 1 of the present embodiment, the number of wiring layers for electrically connecting the memory cells 11 to the drive circuits 70 and 71 can be reduced to half the number of wiring layers of the semiconductor storage device 100.

FIG. 5A illustrates a plan view of another layout of contacts. FIG. 5B illustrates a plan view of still another layout of contacts.

In FIG. 5A, the contacts 40 connected to the cell wirings 20 a arranged side by side in the Y direction are alternately arranged in the hook-up regions 50 and the hook-up regions 51. In addition, the contacts 41 connected to the cell wirings 20 b arranged side by side in the Y direction are alternately arranged in the hook-up regions 50 and the hook-up regions 51. In addition, in the hook-up regions 50 and the hook-up regions 51, the contacts 40 and the contacts 41 are arranged opposite to each other in the Y direction.

In FIG. 5B, the contacts 40 connected to the cell wirings 20 a arranged side by side in the Y direction are alternately arranged in the hook-up regions 50 and the hook-up regions 51. In addition, the contacts 41 connected to the cell wirings 20 b arranged side by side in the Y direction are alternately arranged in the hook-up regions 50 and the hook-up regions 51. Meanwhile, in the hook-up regions 50 and the hook-up regions 51, the contacts 40 and the contacts 41 are arranged in a shifted manner in the X direction.

Even when the contacts 40 and the contacts 41 are arranged as in the layout shown in FIG. 5A or FIG. 5B, the connection wirings 60 and 61 connected to respective contacts can be drawn to regions below the cell array 10, or below both the cell array 10 and the cell array 12, and can be formed in the same wiring layer. Therefore, the number of wiring layers can be reduced.

Second Embodiment

FIG. 6 is a diagram schematically illustrating a cross-sectional structure of a semiconductor storage device according to a second embodiment. Elements similar to those of the semiconductor storage device 1 according to the above-described first embodiment are attached with the same reference numerals, and detailed description thereof will be omitted.

Four wiring layers D0 to D3 are provided in a semiconductor storage device 2 shown in FIG. 6. Each wiring layer includes connection wirings 60 and connection wirings 61. The connection wirings 60 are connected to contacts 40 provided in a hook-up region 51. The connection wirings 61 are connected to contacts 41 provided in the same hook-up region 51 as the contacts 40. The contacts 40 are commonly connected to a plurality of cell wirings 20 a of odd-numbered layers, and the contacts 41 are connected to cell wirings 20 b of an even-numbered layer.

In addition, the connection wirings 60 are electrically connected to drive circuits 70 through transistor wirings 80, and the connection wirings 61 are electrically connected to drive circuits 71 through transistor wirings 81.

The drive circuits 70 are disposed in a region where memory cells 11 are provided, that is, in a region below a cell array 10. The drive circuits 70 include a selection circuit 70 a and a non-selection circuit 70 b. The selection circuit 70 a includes a plurality of selection transistors 72 a, and the non-selection circuit 70 b has a plurality of non-selection transistors 72 b. Each selection transistor 72 a is energized when a memory cell 11 of an odd-numbered layer is selected. Each non-selection transistor 72 b is energized when memory cells 11 of odd-numbered layers are not selected.

In the present embodiment, the selection circuit 70 a is disposed closer to the contacts 40 than the non-selection circuit 70 b. In other words, a wiring length between each contact 40 and the selection circuit 70 a is shorter than that between each contact 40 and the non-selection circuit 70 b. In addition, an input current of the selection transistor 72 a is larger than that of the non-selection transistor 72 b. Therefore, since the selection circuit 70 a and the non-selection circuit 70 b are arranged as described above, electric resistance of a current path to the selection transistor 72 a, through which a relatively large current flows, can be reduced.

The drive circuits 71 include a selection circuit 71 a and a non-selection circuit 71 b. Similarly to the selection circuit 70 a and the non-selection circuit 70 b, the selection circuit 71 a and the non-selection circuit 71 b have a plurality of selection transistors 72 a and a plurality of non-selection transistors 72 b, respectively.

In the present embodiment, the selection circuit 71 a is disposed in the hook-up region 51, and the non-selection circuit 71 b is disposed outside the hook-up region 51. Accordingly, the selection circuit 71 a is disposed closer to the contacts 41 than the non-selection circuit 71 b.

As a result, electric resistance of a current path to the selection transistor 72 a, through which a relatively large current flows, can be reduced.

FIG. 7 is a diagram schematically illustrating a cross-sectional structure of a semiconductor storage device 200 according to a second comparative example.

Elements similar to those of the semiconductor storage device 2 according to the above-described second embodiment are attached with the same reference numerals, and detailed description thereof will be omitted.

In the semiconductor storage device 200 shown in FIG. 7, a wiring layer D4 and a wiring layer D5 are provided in addition to the wiring layers D0 to D3. The wiring layer D2 and the wiring layer D3 include the connection wirings 61. In addition, the wiring layer D4 and the wiring layer D5 include the connection wirings 60.

Further, in the semiconductor storage device 200, the selection circuit 70 a and the selection circuit 71 a are disposed in a region where the memory cells 11 are provided, that is, in the region below the cell array 10. The non-selection circuit 70 b and the non-selection circuit 71 b are disposed in the hook-up region 51.

In the semiconductor storage device 200 according to the present comparative example, the connection wirings 60 and the connection wirings 61 are separately provided in different wiring layers. Therefore, the four wiring layers are required in order to electrically connect the memory cells 11 to the drive circuits 70 and 71. In addition, in the semiconductor storage device 200, the selection circuits 70 a and 71 a are farther from the contacts 40 and 41 than the non-selection circuits 70 b and 71 b.

To the contrary, in the semiconductor storage device shown in FIG. 6, the connection wirings 60 and the connection wirings 61 are provided in the same wiring layer. That is, the connection wirings 60 and the connection wirings 61 share the same wiring layer. Therefore, in the semiconductor storage device 2 of the present embodiment, the number of wiring layers for electrically connecting the memory cells 11 with the drive circuits 70 and 71 can be reduced.

In addition, in the present embodiment, by providing the selection circuits 70 a and 71 a near the contacts 40 and 41, electric resistance of a current path to the selection transistor 72 a, through which a relatively large current flows, can be reduced.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. 

What is claimed is:
 1. A semiconductor storage device, comprising: first, second, and third wiring layers, each including a plurality of first wirings extending in a first direction and arranged side by side in a second direction perpendicular to the first direction; fourth and fifth wiring layers, each including a plurality of second wirings extending in the second direction and arranged side by side in the first direction, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers; a memory cell array having a plurality of memory cells formed at intersections of the first and second wirings of adjacent wiring layers; a first contact electrically connected to a first wiring of the first wiring layer, in a hook-up region; a second contact electrically connected to a first wiring of the second wiring layer, in the hook-up region; a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring; a first drive circuit electrically connected to the first connection wiring; and a second drive circuit electrically connected to the second connection wiring.
 2. The semiconductor storage device according to claim 1, wherein the first contact is electrically connected to a first end of the first connection wiring, and the first drive circuit is electrically connected to a second end of the first connection wiring, and the second contact is electrically connected to a first end of the second connection wiring, and the second drive circuit is electrically connected to a second end of the second connection wiring.
 3. The semiconductor storage device according to claim 2, wherein the first connection wiring extends away from the first contact in the sixth wiring layer and the second connection wiring extends away from the second contact in the sixth wiring layer in opposite directions, such that the first ends of the first and second connection wirings are between the second end of the first connection wiring and the second end of the second connection wiring.
 4. The semiconductor storage device according to claim 3, wherein the first contact and the second contact extend in a third direction that is perpendicular to the first and second directions and are aligned along the second direction.
 5. The semiconductor storage device according to claim 3, wherein the first drive circuit and the second drive circuit each includes a selection circuit that is to be energized for selected memory cells, and a non-selection circuit that is to be energized for non-selected memory cells, and the selection circuit is disposed closer to the first contact or the second contact than the non-selection circuit.
 6. The semiconductor storage device according to claim 5, wherein the hook-up region includes a first hook-up region and a second hook-up region respectively located on opposite sides of the memory cell array, the first connection wiring is electrically connected to the first contact in the first hook-up region, and the second connection wiring is electrically connected to the second contact in the second hook-up region.
 7. The semiconductor storage device according to claim 5, wherein the non-selection circuit of the first drive circuit, the selection circuit of the first drive circuit, the selection circuit of the second drive circuit, and the non-selection circuit of the second drive circuit are arranged in this order along the first direction.
 8. The semiconductor storage device according to claim 7, wherein the sixth wiring layer is below the first through fifth wiring layers, and the first and second drive circuits are below the sixth wiring layer.
 9. The semiconductor storage device according to claim 1, wherein the first drive circuit includes a first selection circuit that is to be energized for selected memory cells, and a first non-selection circuit that is to be energized for non-selected memory cells, the second drive circuit includes a second selection circuit that is to be energized for selected memory cells, and a second non-selection circuit that is to be energized for non-selected memory cells, the first non-selection circuit is disposed below the memory cell array, the second non-selection circuit is disposed below another memory cell array, and the first selection circuit and the second selection circuit are between the first non-selection circuit and the second non-selection circuit.
 10. The semiconductor storage device according to claim 1, wherein the first wirings are bit lines and the second wirings are word lines.
 11. A semiconductor storage device of a cross-point type, comprising: a plurality of bit line and word line wiring layers that are alternately stacked in a first direction; a memory cell array having a plurality of memory cells formed at intersections of the bit line and word line wirings of adjacent wiring layers; a first contact electrically connected to a first bit line wiring in a hook-up region; a second contact electrically connected to a second bit line wiring in the hook-up region; a connection wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring; a first drive circuit electrically connected to the first connection wiring; and a second drive circuit electrically connected to the second connection wiring, wherein the plurality of bit line and word line wiring layers include first and second bit line wiring layers, and a word line wiring layer between the first and second bit line wiring layers, and the first contact is electrically connected to a bit line wiring in the first bit line wiring layer and the second contact is electrically connected to a bit line wiring in the second bit line wiring layer.
 12. The semiconductor storage device according to claim 11, wherein the first contact is electrically connected to a first end of the first connection wiring, and the first drive circuit is electrically connected to a second end of the first connection wiring, and the second contact is electrically connected to a first end of the second connection wiring, and the second drive circuit is electrically connected to a second end of the second connection wiring.
 13. The semiconductor storage device according to claim 12, wherein the first connection wiring extends away from the first contact in the connection wiring layer and the second connection wiring extends away from the second contact in the connection wiring layer in opposite directions, such that the first ends of the first and second connection wirings are between the second end of the first connection wiring and the second end of the second connection wiring.
 14. The semiconductor storage device according to claim 13, wherein the first contact and the second contact extend in the first direction and are aligned along a direction that is perpendicular to the first direction.
 15. The semiconductor storage device according to claim 13, wherein the first drive circuit and the second drive circuit each includes a selection circuit that is to be energized for selected memory cells, and a non-selection circuit that is to be energized for non-selected memory cells, and the selection circuit is disposed closer to the first contact or the second contact than the non-selection circuit.
 16. The semiconductor storage device according to claim 15, wherein the hook-up region includes a first hook-up region and a second hook-up region respectively located on opposite sides of the memory cell array, the first connection wiring is electrically connected to the first contact in the first hook-up region, and the second connection wiring is electrically connected to the second contact in the second hook-up region.
 17. The semiconductor storage device according to claim 15, wherein the non-selection circuit of the first drive circuit, the selection circuit of the first drive circuit, the selection circuit of the second drive circuit, and the non-selection circuit of the second drive circuit are arranged in this order along a direction that is perpendicular to the first direction.
 18. The semiconductor storage device according to claim 17, wherein the connection wiring layer is below the bit line and word line wiring layers, and the first and second drive circuits are below the connection wiring layer.
 19. The semiconductor storage device according to claim 11, wherein the first drive circuit includes a first selection circuit that is to be energized for selected memory cells, and a first non-selection circuit that is to be energized for non-selected memory cells, the second drive circuit includes a second selection circuit that is to be energized for selected memory cells, and a second non-selection circuit that is to be energized for non-selected memory cells, the first non-selection circuit is disposed below the memory cell array, the second non-selection circuit is disposed below another memory cell array, and the first selection circuit and the second selection circuit are between the first non-selection circuit and the second non-selection circuit.
 20. The semiconductor storage device according to claim 11, wherein the memory cells include a first memory cell electrically connected at a first end to a bit line wiring of the first bit line wiring layer and a second memory cell electrically connected at a first end to a bit line wiring of the second bit line wiring layer, and a word line wiring of the word line wiring layer is electrically connected to a second end of the first memory cell and a second end of the second memory cell. 